$97
IEEE 1364-2005
2006
IEEE Standard for Verilog Hardware Description Language
- Format:
- Language(s) :
- Published :
- English
- 04/07/2006
Revision Standard – Superseded.
The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language. (Supersedes IEEE Std 1364-2001. Superseded by IEEE Std 1800-2009).
| IEEE 1364-2005 | |
|---|---|
| STANDARD INFO: | |
| Standard Name | IEEE 1364-2005 |
| Scope | IEEE Standard for Verilog Hardware Description Language |
| Publisher | IEEE - IEEE |
| Languages | English |
| State | |
| Publication Year | 2006 |
| Most recent Version | MOST RECENT |
| Whether to be replaced | |
| Addendum | |
| FILE INFO: | |
| File Size | 1 file , 5.9 MB |
| ISBN(s) | 9780738148519 |
| Note | This product is unavailable in Russia, Belarus |
| Number of Pages | 590 |
| Product Code(s) | STDSU95395 |
| Published | 04/07/2006 |
| IEEE 1364-2005 | ||
|---|---|---|
| History | Publisher Year | |
| IEEE 1800-2009 | 2009 | |
| IEEE 1364-2005 | 2006 | Current |
| IEEE 1800-2005 | 2005 |
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